參數(shù)資料
型號: MPC8560PXAQFD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁數(shù): 55/104頁
文件大小: 1244K
代理商: MPC8560PXAQFD
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
54
Freescale Semiconductor
PCI/PCI-X
SYSCLK to output high impedance
tPCKHOZ
14
ns
2, 3, 10
Input setup to SYSCLK
tPCIVKH
3.0
ns
2, 4, 9
Input hold from SYSCLK
tPCIXKH
0
ns
2, 4, 9
REQ64 to HRESET 9 setup time
tPCRVRH
10
× tSYS
clocks
5, 6, 10
HRESET to REQ64 hold time
tPCRHRX
050
ns
6, 10
HRESET high to first FRAME assertion
tPCRHFV
10
clocks
7, 10
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the valid state
(V) relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI/PCI-X timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal
(F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
6. The setup and hold time is with respect to the rising edge of HRESET.
7. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
Bus Specifications.
8. The reset assertion timing requirement for HRESET is 100
μs.
9. Guaranteed by characterization.
10.Guaranteed by design.
Table 43. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
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MPC8560PX833LD 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
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