參數(shù)資料
型號: MPC8567ECVTAUJJA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023
封裝: 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 104/139頁
文件大小: 1449K
代理商: MPC8567ECVTAUJJA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
67
High-Speed Serial Interfaces (HSSI)
Figure 44 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8568 SerDes reference clock
input’s DC requirement.
Figure 44. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 45 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8568 SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-
Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
Figure 45. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
50
Ω
50
Ω
SD_REF_CLK
Clock Driver
100
Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
MPC8568E
CLK_Out
50
Ω
50
Ω
SD_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVDS CLK Driver Chip
10 nF
MPC8568E
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