參數(shù)資料
型號: MPC8567EVTAQGG
廠商: Freescale Semiconductor
文件頁數(shù): 72/139頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準包裝: 24
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
38
Freescale Semiconductor
Ethernet Interface and MII Management
Duty cycle for 10BASE-T and 100BASE-TX 3, 4
tRGTH/tRGT
5
40
50
60
%
Rise time (20%–80%)
tRGTR
5
—0.75
1.5
ns
Fall time (20%–80%)
tRGTF
5
—0.75
1.5
ns
EC_GTX_CLK125 clock rise time (20%-80%)
tG125R
—0.75
1.5
ns
EC_GTX_CLK125 clock fall time (80%-20%)
tG125F
—0.75
1.5
ns
EC_GTX_CLK125 duty cycle6
tG125H/tG125
47
53
ns
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to
represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note
also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than
1.5 ns will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains
as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Guaranteed by characterization
6. EC_GTX_CLK125 is used to generate GTX_CLK for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125
duty cycle can be loosen from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK.
Table 34. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 2.5 V ± 5%.
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