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| 型號(hào)： | MPC8567VTAUJJ |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023 |
| 封裝： | 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCPBGA-1023 |
| 文件頁(yè)數(shù)： | 36/140頁(yè) |
| 文件大?。?/td> | 1456K |
| 代理商： | MPC8567VTAUJJ |
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
130
Freescale Semiconductor
System Design Information
Thermagon Inc.
888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8568E.
25.1
System Clocking
This device includes six PLLs, as follows:
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 23.2, “CCB/SYSCLK PLL Ratio.”
2. The e500 core PLL generates the core clock using the platform clock as the input. The frequency
ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in Section 23.3, “e500 Core PLL Ratio.”
3. The PCI PLL generates the clocking for the PCI bus
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes block.
6. QE PLL generates the QE clock from the externally supplied SYSCLK.
25.2
Power Supply Design and Sequencing
25.2.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS, AVDD_CE respectively). The AVDD
level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 73, one to each of the
AVDD type pins. By providing independent filters to each PLL the opportunity to cause noise injection
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
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