參數(shù)資料
型號(hào)： MPC8568CVTANGGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA1023
封裝： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCPBGA-1023
文件頁數(shù)： 114/140頁
文件大?。?/td> 1456K
代理商： MPC8568CVTANGGA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
75
PCI Express
TRX-EYE
Minimum
Receiver Eye
Width
0.4
—
UI
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as TRX-MAX-JITTER =
1 – TRX-EYE= 0.6 UI.
See Notes 2 and 3.
TRX-EYE-MEDIAN-to-MAX
-JITTER
Maximum time
between the jitter
median and
maximum
deviation from
the median.
—
0.3
UI
Jitter is defined as the measurement variation
of the crossing points (VRX-DIFFp-p = 0 V) in
relation to a recovered TX UI. A recovered TX
UI is calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the TX UI. See Notes 2, 3 and 7.
VRX-CM-ACp
AC Peak
Common Mode
Input Voltage
——
150
mV
VRX-CM-ACp = |VRXD+ + VRXD-|/2 – VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2
See Note 2
RLRX-DIFF
Differential
Return Loss
10
—
dB
Measured over 50 MHz to 1.25 GHz with the
D+ and D- lines biased at +300 mV and -300
mV, respectively.
See Note 4
RLRX-CM
Common Mode
Return Loss
6
—
dB
Measured over 50 MHz to 1.25 GHz with the
D+ and D- lines biased at 0 V. See Note 4
ZRX-DIFF-DC
DC Differential
Input Impedance
80
100
120
Ω
RX DC Differential mode impedance. See
Note 5
ZRX-DC
DC Input
Impedance
40
50
60
Ω
Required RX D+ as well as D- DC Impedance
(50 ± 20% tolerance). See Notes 2 and 5.
ZRX-HIGH-IMP-DC
Powered Down
DC Input
Impedance
200 k
—
Ω
Required RX D+ as well as D- DC Impedance
when the Receiver terminations do not have
power. See Note 6.
VRX-IDLE-DET-DIFFp-p
Electrical Idle
Detect Threshold
65
—
175
mV
VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ -VRX-D-|
Measured at the package pins of the Receiver
TRX-IDLE-DET-DIFF-
ENTERTIME
Unexpected
Electrical Idle
Enter Detect
Threshold
Integration Time
—
10
ms
An unexpected Electrical Idle (VRX-DIFFp-p <
VRX-IDLE-DET-DIFFp-p) must be recognized no
longer than TRX-IDLE-DET-DIFF-ENTERING to
signal an unexpected idle condition.
Table 52. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Units
Comments
相關(guān)PDF資料
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MPC8567VTAUJJ 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023
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