參數(shù)資料
型號(hào)： MPC8568ECVTAUJJA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023
封裝： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 111/139頁
文件大小： 1449K
代理商： MPC8568ECVTAUJJA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
73
PCI Express
14.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 49 is specified using the passive compliance/test measurement load (see
Figure 51) in place of any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
RLTX-CM
Common Mode
Return Loss
6
—
dB
Measured over 50 MHz to 1.25 GHz. See Note 4
ZTX-DIFF-DC
DC Differential
TX Impedance
80
100
120
Ω
TX DC Differential mode Low Impedance
ZTX-DC
Transmitter DC
Impedance
40
—
Ω
Required TX D+ as well as D- DC Impedance during all
states
LTX-SKEW
Lane-to-Lane
Output Skew
—
500 +
2 UI
ps
Static skew between any two Transmitter Lanes within a
single Link
CTX
AC Coupling
Capacitor
75
—
200
nF
All Transmitters shall be AC coupled. The AC coupling is
required either within the media or within the
transmitting component itself. See note 8.
Tcrosslink
Crosslink
Random
Timeout
0
—
1
ms
This random timeout helps resolve conflicts in crosslink
configuration by eventually resulting in only one
Downstream and one Upstream Port. See Note 7.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 51 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 49)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50
Ω to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 51). Note that the series capacitors
CTX is optional for the return loss measurement.
5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 51 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
8. MPC8568E SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
Table 51. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Units
Comments
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