參數(shù)資料
型號: MPC8569ECVTANKG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 7/126頁
文件大?。?/td> 2847K
代理商: MPC8569ECVTANKG
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Enhanced Local Bus Controller
Freescale Semiconductor
104
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by tacs (0, , , 1, 1 + , 1 + , 2, 3 cycles), so the final delay is tacs + tLBKHOV.
The following figure shows how the AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.
Figure 58. GPCM Output Timing Diagram (PLL Enabled)
2.15.2.3
Enhanced Local Bus AC Timing Specifications for PLL Bypass Mode
All output signal timings are relative to the falling edge of any LCLKs for PLL bypass mode. The external circuit must use the
rising edge of the LCLKs to latch the data.
All input timings except LUPWAIT/LFRB are relative to the rising edge of LCLKs. LUPWAIT/LFRB are relative to the falling
edge of LCLKs.
tarcs +tLBKHOV
LSYNC_IN
LAD[0:31]
LBCTL
tLBONOT
LCS_B
LGPL2/LOE_B
address
taddr
taoe +tLBKHOV
LWE_B
tawcs +tLBKHOV
tLBONOT
address
taddr
tawe+tLBKHOV
tLBKHOX
trc
toen
read data
write data
twen
twc
write
read
LALE
1 t
addr is programmable and determined by LCRR[EADC] and ORx[EAD].
2 t
arcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. Refer to reference manual.
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