參數(shù)資料
型號(hào)： MPC8569ECVTAQLJA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 8/126頁
文件大?。?/td> 2847K
代理商： MPC8569ECVTAQLJA
Enhanced Local Bus Controller
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
105
The following table describes the timing specifications of the enhanced local bus interface at BVDD = 3.3, 2.5, and 1.8 V DC
with PLL disabled.
Table 66. Enhanced Local Bus Timing Specifications (BVDD = 3.3 V, 2.5 V, and 1.8 V)—PLL Bypassed
For recommended operating conditions, see Table 3
Parameter
Symbol1
Min
Max
Unit
Notes
Enhanced local bus cycle time
tLBK
12
—
ns
—
Enhanced local bus duty cycle
tLBKH/tLBK
45
55
%
6
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—150
ps
2
Input setup
(except LUPWAIT/LFRB)
tLBIVKH
6.5
—
ns
—
Input hold
(except LUPWAIT/LFRB)
tLBIXKH
1—
ns
—
Input setup
(for LUPWAIT/LFRB)
tLBIVKL
6.5
—
ns
—
Input hold
(for LUPWAIT/LFRB)
tLBIXKL
1—
ns
—
Output delay
(Except LALE)
tLBKLOV
—1.5
ns
—
Output hold
(Except LALE)
tLBKLOX
–3.5
—
ns
5
Enhanced local bus clock to output high
impedance for LAD/LDP
tLBKLOZ
—2
ns
3
LALE output negation to LAD/LDP output
transition (LATCH hold time)
tLBONOT
1 – 1 ns
(LBCR[AHD] = 0)
1/2 – 1 ns
(LBCR[AHD] = 1)
—
eLBC
controller
clock
cycle
(=1
platform
clock
cycle in
ns)
4
Notes:
1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.
2. Skew measured between different LCLK signals at BVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined
by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not
the external LCLK. LCLK cycle = eLBC controller clock cycle
× LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults
to 0 and eLBC runs at maximum hold time.
5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
6. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
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參數(shù)描述
MPC8569ECVTAQLJB 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569E XT1067/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569E-MDS-PB 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8569 MDS PROCESSOR BD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8569EVTANKGB 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 800MHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569EVTAQLJB 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 1GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569EVTAUNLB 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 1.33GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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