參數(shù)資料
型號: MPC8569EVTANKGB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 89/126頁
文件大?。?/td> 2847K
代理商: MPC8569EVTANKGB
Ethernet Interface
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
65
The following figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
Figure 26. RGMII and RTBI AC Timing and Multiplexing Diagrams
2.6.4
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of MPC8569E as shown in Figure 27,
where CTX is the external (on board) AC-coupled capacitor. Each output pin of the SerDes transmitter differential pair features
50-
Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ωon-die termination to GND. The
reference circuit of the SerDes transmitter and receiver is shown in Figure 45.
2.6.4.1
SGMII DC Electrical Characteristics
This section discusses the electrical characteristics for the SGMII interface.
2.6.4.1.1
DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.9.2.3, “DC Level
GTX_CLK
tRGT
tRGTH
tSKRGT_TX
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RX_CLK
(At PHY)
tSKRGT_RX
tSKRGT_TX
tRGTH
tRGT
GTX_CLK
(At Receiver)
RXD[8:5][3:0]
RXD[7:4][3:0]
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