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| 型號(hào)： | MPC8569EVTAQLJA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783 |
| 文件頁(yè)數(shù)： | 123/126頁(yè) |
| 文件大?。?/td> | 2847K |
| 代理商： | MPC8569EVTAQLJA |
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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
I2C
Freescale Semiconductor
96
The following figure provides the AC test load for the I2C.
Figure 49. I2C AC Test Load
The following figure shows the AC timing diagram for the I2C bus.
Figure 50. I2C Bus AC Timing Diagram
Noise margin at the LOW level for each connected
device (including hysteresis)
VNL
0.1
× OVDD
—V
—
Noise margin at the HIGH level for each connected
device (including hysteresis)
VNH
0.2
× OVDD
—V
—
Capacitive load for each bus line
Cb
—
400
pF
—
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the
I2C Frequency Divider Ratio for SCL.”
3. As a transmitter, the MPC8659E provides a delay time of at least 300 ns for the SDA signal (referred to as the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the MPC8569E acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the
load on SCL and SDA are balanced, the MPC8569E does not generate an unintended START or STOP condition. Therefore,
the 300 ns SDA output delay time is not a concern. If under some rare condition, the 300 ns SDA output delay time is required
for the MPC8569E as transmitter, application note AN2919, referred to in note 4 below, is recommended.
4. The maximum tI2OVKL must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
Table 57. I2C AC Timing Specifications (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2SXKL
tI2CL
tI2CH
tI2DXKL,tI2OVKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
PS
tI2KHDX
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|---|---|
| MPC8569EVTAQLJB | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 1GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569EVTAUNLB | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 1.33GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569VJAUNLB | 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 1333MHZ 783FCBGA |
| MPC8569VTANKGB | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 ST 800/600/400 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569VTAQLJB | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 ST 1067/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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