參數(shù)資料
型號： MPC8569VTAUNLA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 62/126頁
文件大?。?/td> 2847K
代理商： MPC8569VTAUNLA
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Overall DC Electrical Characteristics
Freescale Semiconductor
40
2.1.1.2
Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths. The values are preliminary
estimates.
2.1.2
Power Sequencing
The MPC8569E requires its power rails to be applied in a specific sequence to ensure proper device operation. These
requirements are as follows for power up:
1.
VDD, AVDD_n, BVDD, LVDDn, OVDD, ScoreVDD, XVDD
2.
GVDD
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
NOTE
While VDD is ramping, current may be supplied from VDD through the MPC8569E to
GVDD. Nevertheless, GVDD from an external supply should follow the sequencing
described above.
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD core supply, the I/Os associated with that I/O
supply may drive a logic one or zero during power up, and extra current may be drawn by the device.
2.1.3
RESET Initialization
This section describes the AC electrical specifications for the RESET timing requirements of the MPC8569E. The following
table describes the specifications for the RESET initialization timing.
Table 4. Output Drive Capability
Driver Type
Programmable Output Impedance (
Ω)
Supply Voltage
Notes
Enhanced local bus interface utilities signals
45
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
—
DDR2 signal
18 (full strength mode)
35 (half strength mode)
GVDD = 1.8 V
1
DDR3 signal
20 (full strength mode)
40 (half strength mode)
GVDD = 1.5 V
1
DUART, EPIC, I2C, JTAG, system control
45
OVDD = 3.3 V
—
Note:
1. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at TJ = 105° C and at GVDD (min). Refer to the
MPC8569 reference manual for the DDR impedance programming procedure through the DDR control driver register 1
(DDRCDR_1).
Table 5. RESET Initialization Timing Specifications
Parameter
Min
Max
Unit
Notes
Required assertion time of HRESET
10
—
SYSCLK
1, 2
Minimum assertion time of TRESET simultaneous to HRESET assertion
25
—
ns
3
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