參數(shù)資料
型號: MPC8572CLVTAULD
廠商: Freescale Semiconductor
文件頁數(shù): 60/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
28
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
7.2
DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface.
8
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet
controller.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—FIFO/GMII/MII/TBI/RGMII/RTBI/RMII
Electrical Characteristics
The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface
(GMII), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent
interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII)
signals except management data input/output (MDIO) and management data clock (MDC), and serial
gigabit media independent interface (SGMII). The RGMII, RTBI and FIFO mode interfaces are defined
for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can operate at both 2.5 V and 3.3V .
The GMII, MII, or TBI interface timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces
follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3
(12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2
(3/20/1998).
The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet Management
The electrical characteristics for SGMII is specified in Section 8.3, “SGMII Interface Electrical
Characteristics.” The SGMII interface conforms (with exceptions) to the Serial-GMII Specification
Version 1.8.
Table 22. DUART AC Timing Specifications
At recommended operating conditions with OVDD of 3.3V ± 5%.
Parameter
Value
Unit
Notes
Minimum baud rate
fCCB/1,048,576
baud
1, 2
Maximum baud rate
fCCB/16
baud
1, 2, 3
Oversample rate
16
1, 4
Notes:
1. Guaranteed by design
2. fCCB refers to the internal platform clock frequency.
3. Actual attainable baud rate is limited by the latency of interrupt processing.
4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
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