1. 參數(shù)資料
    型號: MPC8572ECLVTAULD
    廠商: Freescale Semiconductor
    文件頁數(shù): 126/138頁
    文件大小: 0K
    描述: MPU POWERQUICC III 1023FCPBGA
    標準包裝: 1
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 1.333GHz
    電壓: 1.1V
    安裝類型: 表面貼裝
    封裝/外殼: 1023-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
    包裝: 托盤
    MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    88
    Freescale Semiconductor
    PCI Express
    16.5
    Receiver Compliance Eye Diagrams
    The RX eye diagram in Figure 56 is specified using the passive compliance/test measurement load (see
    Figure 57) in place of any real PCI Express RX component.
    Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement
    load (see Figure 57) is larger than the minimum Receiver eye diagram measured over a range of systems
    at the input Receiver of any real PCI Express component. The degraded eye diagram at the input Receiver
    is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI
    Express component to vary in impedance from the compliance/test measurement load. The input Receiver
    eye diagram is implementation specific and is not specified. RX component designer should provide
    additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in
    Figure 56) expected at the input Receiver based on some adequate combination of system simulations and
    the Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned
    in time using the jitter median to locate the center of the eye diagram.
    The eye diagram must be valid for any 250 consecutive UIs.
    A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
    created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
    UI.
    NOTE
    The reference impedance for return loss measurements is 50. to ground for
    both the D+ and D- line (that is, as measured by a Vector Network Analyzer
    with 50. probes—see Figure 57). Note that the series capacitors, CTX, are
    optional for the return loss measurement.
    Figure 56. Minimum Receiver Eye Timing and Voltage Compliance Specification
    VRX-DIFF = 0 mV
    (D+ D– Crossing Point)
    VRX-DIFF = 0 mV
    (D+ D– Crossing Point)
    VRX-DIFFp-p-MIN > 175 mV
    0.4 UI = TRX-EYE-MIN
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    MPC8572ECLVTAULE 功能描述:微處理器 - MPU R211 Enc NoPb 1333LP Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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