
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
103
Package Description
D2_MCAS
Column Address Strobe
AD1
O
GVDD
—
D2_MRAS
Row Address Strobe
AA1
O
GVDD
—
D2_MCKE[0:3]
Clock Enable
L3, L1, K1, K2
O
GVDD
11
D2_MCS[0:3]
Chip Select
AB1, AG2, AC1, AH2
O
GVDD
—
D2_MCK[0:5]
Clock
V4, F7, AJ3, V2, E7,
AG4
OGVDD
—
D2_MCK[0:5]
Clock Complements
V1, F8, AJ4, U1, E6,
AG5
OGVDD
—
D2_MODT[0:3]
On Die Termination
AE1, AG1, AE2, AH1
O
GVDD
—
D2_MDIC[0:1]
Driver Impedance Calibration
F1, G1
I/O
GVDD
25
Local Bus Controller Interface
LAD[0:31]
Muxed Data/Address
M22, L22, F22, G22,
F21, G21, E20, H22,
K22, K21, H19, J20,
J19, L20, M20, M19,
E22, E21, L19, K19,
G19, H18, E18, G18,
J17, K17, K14, J15,
H16, J14, H15, G15
I/O
BVDD
34
LDP[0:3]
Data Parity
M21, D22, A24, E17
I/O
BVDD
—
LA[27]
Burst Address
J21
O
BVDD
5, 9
LA[28:31]
Port Address
F20, K18, H20, G17
O
BVDD
5, 7, 9
LCS[0:4]
Chip Selects
B23, E16, D20, B25,
A22
OBVDD
10
LCS[5]/DMA2_DREQ[1]
Chip Selects / DMA Request
D19
I/O
BVDD
1, 10
LCS[6]/DMA2_DACK[1]
Chip Selects / DMA Ack
E19
O
BVDD
1, 10
LCS[7]/DMA2_DDONE[1]
Chip Selects / DMA Done
C21
O
BVDD
1, 10
LWE[0]/LBS[0]/LFWE
Write Enable / Byte Select
D17
O
BVDD
5, 9
LWE[1]/LBS[1]
Write Enable / Byte Select
F15
O
BVDD
5, 9
LWE[2]/LBS[2]
Write Enable / Byte Select
B24
O
BVDD
5, 9
LWE[3]/LBS[3]
Write Enable / Byte Select
D18
O
BVDD
5, 9
LALE
Address Latch Enable
F19
O
BVDD
5, 8, 9
LBCTL
Buffer Control
L18
O
BVDD
5, 8, 9
LGPL0/LFCLE
UPM General Purpose Line 0 /
Flash Command Latch Enable
J13
O
BVDD
5, 9
LGPL1/LFALE
UPM General Purpose Line 1/
Flash Address Latch Enable
J16
O
BVDD
5, 9
Table 76. MPC8572E Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes