參數(shù)資料
型號(hào): MPC8572EPXAVND
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, PLASTIC, FCBGA-1023
文件頁(yè)數(shù): 31/138頁(yè)
文件大?。?/td> 1502K
代理商: MPC8572EPXAVND
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
126
Freescale Semiconductor
System Design Information
Figure 62 shows the PLL power supply filter circuits.
Figure 62. PLL Power Supply Filter Circuit
NOTE
It is recommended to have the minimum number of vias in the AVDD trace
for board layout. For example, zero vias might be possible if the AVDD filter
is placed on the component side. One via might be possible if it is placed on
the opposite of the component side. In addition, all traces for AVDD and the
filter components should be low impedance, 10 to 15 mils wide and short.
This includes traces going to GND and the supply rails they are filtering.
The AVDD_SRDSn signal provides power for the analog portions of the SerDesn PLL. To ensure stability
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AVDD_SRDSn ball to ensure it filters out as much noise as possible. The ground connection should be near
the AVDD_SRDSn ball. The 0.003-F capacitor is closest to the ball, followed by the two 2.2 F
capacitors, and finally the 1
Ω resistor to the board supply plane. The capacitors are connected from
AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
frequency. All traces should be kept short, wide and direct.
Figure 63. SerDes PLL Power Supply Filter
Note the following:
AVDD_SRDSn should be a filtered version of SVDD_SRDSn.
Signals on the SerDesn interface are fed from the XVDD_SRDSn power plane.
21.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8572E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin
of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD,
VDD
AVDD
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
2.2 F 1
0.003 F
GND
1.0
Ω
AVDD_SRDSn
1. An 0805 sized capacitor is recommended for system initial bring-up.
SVDD_SRDSn
2.2 F 1
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