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    參數(shù)資料
    型號(hào): MPC8572LVTAULE
    廠商: Freescale Semiconductor
    文件頁數(shù): 95/138頁
    文件大?。?/td> 0K
    描述: MPU POWERQUICC III 1023FCPBGA
    標(biāo)準(zhǔn)包裝: 1
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 1.333GHz
    電壓: 1.1V
    安裝類型: 表面貼裝
    封裝/外殼: 1023-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
    包裝: 托盤
    MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    6
    Freescale Semiconductor
    Overview
    — Three protocol engines available on a per-chip select basis:
    – General-purpose chip select machine (GPCM)
    – Three user programmable machines (UPMs)
    – NAND Flash control machine (FCM)
    — Parity support
    — Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
    Four enhanced three-speed Ethernet controllers (eTSECs)
    — Three-speed support (10/100/1000 Mbps)
    — Four IEEE Std 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers
    — Support for various Ethernet physical interfaces:
    – 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, RGMII, and SGMII
    – 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII
    — Flexible configuration for multiple PHY interface configurations
    — TCP/IP acceleration and QoS features available
    – IP v4 and IP v6 header recognition on receive
    – IP v4 header checksum verification and generation
    – TCP and UDP checksum verification and generation
    – Per-packet configurable acceleration
    – Recognition of VLAN, stacked (Q-in-Q) VLAN, 802.2, PPPoE session, MPLS stacks, and
    ESP/AH IP-security headers
    – Supported in all FIFO modes
    — Quality of service support:
    – Transmission from up to eight physical queues
    – Reception to up to eight physical queues
    — Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
    – IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
    software-programmed PAUSE frame generation and recognition)
    — Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
    IEEE Std 802.1 virtual local area network (VLAN) tags and priority
    — VLAN insertion and deletion
    – Per-frame VLAN control word or default VLAN for each eTSEC
    – Extracted VLAN control word passed to software separately
    — Retransmission following a collision
    — CRC generation and verification of inbound/outbound frames
    — Programmable Ethernet preamble insertion and extraction of up to 7 bytes
    — MAC address recognition:
    – Exact match on primary and virtual 48-bit unicast addresses
    – VRRP and HSRP support for seamless router fail-over
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