參數(shù)資料
型號: MPC8572LVTAVNE
廠商: Freescale Semiconductor
文件頁數(shù): 4/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023FCPBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應商設備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
101
Package Description
6. Parallelism measurement shall exclude any effect of mark on top surface of package.
18.3
Pinout Listings
Table 76 provides the pin-out listing for the MPC8572E 1023 FC-PBGA package.
Table 76. MPC8572E Pinout Listing
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
DDR SDRAM Memory Interface 1
D1_MDQ[0:63]
Data
D15, A14, B12, D12,
A15, B15, B13, C13,
C11, D11, D9, A8, A12,
A11, A9, B9, F11, G12,
K11, K12, E10, E9,
J11, J10, G8, H10, L10,
M11, F10, G9, K9, K8,
AC6, AC7, AG8, AH9,
AB6, AB8, AE9, AF9,
AL8, AM8, AM10,
AK11, AH8, AK8, AJ10,
AK10, AL12, AJ12,
AL14, AK14, AL11,
AM11, AK13, AM14,
AM15, AJ16, AL18,
AM18, AJ15, AL15,
AK17, AM17
I/O
GVDD
D1_MECC[0:7]
Error Correcting Code
M10, M7, R8, T11, L12,
L11, P9, R10
I/O
GVDD
D1_MAPAR_ERR
Address Parity Error
P6
I
GVDD
D1_MAPAR_OUT
Address Parity Out
W6
O
GVDD
D1_MDM[0:8]
Data Mask
C14, A10, G11, H9,
AD7, AJ9, AM12,
AK16, N11
OGVDD
D1_MDQS[0:8]
Data Strobe
A13, C10, H12, J7,
AE8, AM9, AM13,
AL17, N9
I/O
GVDD
D1_MDQS[0:8]
Data Strobe
D14, B10, H13, J8,
AD8, AL9, AJ13,
AM16, P10
I/O
GVDD
D1_MA[0:15]
Address
Y7, W8, U6, W9, U7,
V8, Y11, V10, T6, V11,
AA10, U9, U10, AD11,
T8, P7
OGVDD
D1_MBA[0:2]
Bank Select
AA7, AA8, R7
O
GVDD
D1_MWE
Write Enable
AC12
O
GVDD
D1_MCAS
Column Address Strobe
AC9
O
GVDD
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