參數(shù)資料
型號: MPC8572VTATLE
廠商: Freescale Semiconductor
文件頁數(shù): 119/138頁
文件大小: 0K
描述: MPU POWERQUICC III 1023FCPBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
81
PCI Express
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
15.2.4.1
Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK are designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not to be used with, and should not be clocked by, a spread spectrum
clock source.
15.3
SerDes Transmitter and Receiver Reference Circuits
Figure 54 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 54. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
(PCI Express, Serial Rapid IO or SGMII) in this document based on the application usage:
Note that external AC Coupling capacitor is required for the above three serial transmission protocols with
the capacitor value defined in specification of each protocol section.
16 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8572E.
50
Ω
50
Ω
Receiver
Transmitter
SD1_TX
n or
SD2_TX
n
SD1_TX
n or
SD2_TX
n
SD1_RX
n or
SD2_RX
n
SD1_RX
n or
SD2_RX
n
50
Ω
50
Ω
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