參數(shù)資料
型號(hào): MPC8572VTAVND
廠商: Freescale Semiconductor
文件頁數(shù): 50/138頁
文件大小: 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
19
DDR2 and DDR3 SDRAM Controller
Table 10 provides the PLL lock times.
6
DDR2 and DDR3 SDRAM Controller
This section describes the DC and AC electrical specifications for the DDR2 and DDR3 SDRAM
controller interface of the MPC8572E. Note that the required GVDD(typ) voltage is 1.8Vor 1.5 V when
interfacing to DDR2 or DDR3 SDRAM, respectively.
6.1
DDR2 and DDR3 SDRAM Interface DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR SDRAM controller of the
MPC8572E when interfacing to DDR2 SDRAM.
Table 10. PLL Lock Times
Parameter/Condition
Symbol
Min
Typical
Max
PLL lock times
100
μs—
Local bus PLL
50
μs—
Table 11. DDR2 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.71
1.89
V
1
I/O reference voltage
MVREFn
0.49
× GVDD
0.51
× GVDD
V2
I/O termination voltage
VTT
MVREFn –0.04
MVREFn +0.04
V
3
Input high voltage
VIH
MVREFn + 0.125
GVDD +0.3
V
Input low voltage
VIL
–0.3
MVREFn – 0.125
V
Output leakage current
IOZ
–50
50
μA4
Output high current (VOUT = 1.420 V)
IOH
–13.4
mA
Output low current (VOUT = 0.280 V)
IOL
13.4
mA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREFn is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREFn may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to that far end signal termination is made and is expected to be
equal to MVREFn. This rail should track variations in the DC level of MVREFn.
4. Output leakage is measured with all outputs disabled, 0 V
VOUT GVDD.
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