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    參數(shù)資料
    型號: MPC860DPCVR50D4
    廠商: Freescale Semiconductor
    文件頁數(shù): 51/78頁
    文件大小: 0K
    描述: IC MPU POWERQUICC 50MHZ 357PBGA
    標(biāo)準(zhǔn)包裝: 44
    系列: MPC8xx
    處理器類型: 32-位 MPC8xx PowerQUICC
    速度: 50MHz
    電壓: 3.3V
    安裝類型: 表面貼裝
    封裝/外殼: 357-BBGA
    供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
    包裝: 托盤
    MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
    Freescale Semiconductor
    55
    CPM Electrical Characteristics
    11.7
    SCC in NMSI Mode Electrical Specifications
    Table 20 provides the NMSI external clock timing.
    Table 21 provides the NMSI internal clock timing.
    Table 20. NMSI External Clock Timing
    Num
    Characteristic
    All Frequencies
    Unit
    Min
    Max
    100
    RCLK1 and TCLK1 width high1
    1 The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.
    1/SYNCCLK
    ns
    101
    RCLK1 and TCLK1 width low
    1/SYNCCLK + 5
    ns
    102
    RCLK1 and TCLK1 rise/fall time
    15.00
    ns
    103
    TXD1 active delay (from TCLK1 falling edge)
    0.00
    50.00
    ns
    104
    RTS1 active/inactive delay (from TCLK1 falling edge)
    0.00
    50.00
    ns
    105
    CTS1 setup time to TCLK1 rising edge
    5.00
    ns
    106
    RXD1 setup time to RCLK1 rising edge
    5.00
    ns
    107
    RXD1 hold time from RCLK1 rising edge2
    2 Also applies to CD and CTS hold time when they are used as external sync signals.
    5.00
    ns
    108
    CD1 setup Time to RCLK1 rising edge
    5.00
    ns
    Table 21. NMSI Internal Clock Timing
    Num
    Characteristic
    All Frequencies
    Unit
    Min
    Max
    100
    RCLK1 and TCLK1 frequency1
    1 The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1.
    0.00
    SYNCCLK/3
    MHz
    102
    RCLK1 and TCLK1 rise/fall time
    ns
    103
    TXD1 active delay (from TCLK1 falling edge)
    0.00
    30.00
    ns
    104
    RTS1 active/inactive delay (from TCLK1 falling edge)
    0.00
    30.00
    ns
    105
    CTS1 setup time to TCLK1 rising edge
    40.00
    ns
    106
    RXD1 setup time to RCLK1 rising edge
    40.00
    ns
    107
    RXD1 hold time from RCLK1 rising edge2
    2 Also applies to CD and CTS hold time when they are used as external sync signals.
    0.00
    ns
    108
    CD1 setup time to RCLK1 rising edge
    40.00
    ns
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