參數(shù)資料
型號: MPC875ZT133
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
封裝: 23 X 23 MM, PLASTIC, BGA-256
文件頁數(shù): 6/84頁
文件大?。?/td> 1352K
代理商: MPC875ZT133
14
MPC875/MPC870 Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Mandatory Reset Configurations
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
VDDL must not exceed VDDH during power up and power down.
VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V.
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate
the maximum potential difference on power down.
Figure 3. Example Voltage Sequencing Circuit
9
Mandatory Reset Configurations
The MPC875/870 requires a mandatory configuration during reset.
If hardware reset configuration word (HRCW) is enabled, the HRCW[DBGC] value needs to be set to
binary X1 in the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot
code after reset. This can be done by asserting the RSTCONF during HRESET assertion.
If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after
reset by negating the RSTCONF during the HRESET assertion.
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured
with the mandatory values in Table 7 in the boot code after the reset is negated.
Table 7. Mandatory Reset Configuration of MPC875/870
Register/Configuration
Field
Value
(binary)
HRCW
(Hardware reset configuration word)
HRCW[DBGC]
X1
SIUMCR
(SIU module configuration register)
SIUMCR[DBGC]
X1
MBMR
(Machine B mode register)
MBMR[GPLB4DIS}
0
VDDH
VDDL
1N5820
MUR420
相關(guān)PDF資料
PDF描述
MPC870ZT133 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
MPC875ZT80 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
MPC880VR80 32-BIT, 80 MHz, RISC PROCESSOR, PBGA357
MPC885CVR133 32-BIT, 133 MHz, RISC PROCESSOR, PBGA357
MPC885ZP66 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357
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