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參數(shù)資料
| 型號(hào)： | MPC9229FN |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | MPC9229FN |
MPC9229 REVISION 3 AUGUST 6, 2009
3
2009 Integrated Device Technology, Inc.
MPC9229 Data Sheet
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
—
Analog
Crystal oscillator interface
fOUT, fOUT
Output
—
LVPECL
Differential clock output
TEST
Output
—
LVCMOS
Test and device diagnosis output
S_LOAD
Input
0
LVCMOS
Serial configuration control input
This inputs controls the loading of the configuration latches with the contents
of the shift register. The latches will be transparent when this signal is high,
thus the data must be stable on the high-to-low transition
P_LOAD
Input
1
LVCMOS
Parallel configuration control input
This input controls the loading of the configuration latches with the content of
the parallel inputs (M and N). The latches will be transparent when this signal
is low, thus the parallel data must be stable on the low-to-high transition of
P_LOAD. P_LOAD is state sensitive
S_DATA
Input
0
LVCMOS
Serial configuration data input
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input
M[0:8]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N)
N is sampled on the low-to-high transition of P_LOAD
OE
Input
1
LVCMOS
Output enable (active high).
The output enable is synchronous to the output clock to eliminate the
possibility of runt pulses on the fOUT output. OE = L low stops fOUT in the logic
low state (fOUT = L, fOUT = H)
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
Table 2. Output Frequency Range and Pll Post-Divider N
N
Output Division
Output Frequency Range
1
0
0
1
200 – 400 MHz
0
1
2
100 – 200 MHz
1
0
4
50 – 100 MHz
1
8
25 – 50 MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9229FNR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Single 28-Pin PLCC T/R |
| MPC9230 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:800 MHz Low Voltage PECL Clock Synthesizer |
| MPC9230AC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 800MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC9230ACR2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 800MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC9230EI | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 800MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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