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參數(shù)資料
| 型號(hào)： | MPC9239EIR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK SYNTH LV PECL 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.5x11.5） |
| 包裝： | 帶卷 (TR) |
DATASHEET
900 MHz Low Voltage LVPECL
Clock Synthesizer
MPC9239
MPC9239
REVISION 2
DECEMBER 18, 2012
1
2012 Integrated Device Technology, Inc.
The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking, and computing applications. With output frequencies from
3.125 MHz to 900 MHz and the support of differential LVPECL output signals
the device meets the needs of the most demanding clock applications.
Features
3.125 MHz to 900 MHz synthesized clock output signal
Differential LVPECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference input
3.3 V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
28 PLCC and 32 LQFP packaging
SiGe Technology
Ambient temperature range 0
C to + 70C
Pin and function compatible to the MC12439
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of
its frequency reference. The frequency of the internal crystal oscillator or exter-
nal reference clock signal is multiplied by the PLL. The VCO within the PLL op-
erates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is
configured by either the serial or parallel interfaces. The crystal oscillator fre-
quency fXTAL, the PLL feedback-divider M and the PLL post-divider N deter-
mine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The
PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be pro-
grammed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios
(1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially
from the output divider, and is capable of driving a pair of transmission lines terminated 50
to VCC – 2.0 V. The positive supply volt-
age for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs
to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On
the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface.
Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating.
The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial
input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration
latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to PROGRAMMING INTER-
FACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial
data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin,
when asserted, will synchronously divide the fOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby
causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back
up to its programmed frequency in four discrete increments.
MPC9239
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
900 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
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| MPC9239FA | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V 900MHz Clock Generator RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC9239FN | 功能描述:IC PECL CLOCK LV 900MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC9239FNR2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92429 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:400 MHz Low Voltage PECL Clock Synthesizer |
| MPC92429AC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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