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參數(shù)資料
| 型號： | MPC9239FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 353K |
| 代理商： | MPC9239FAR2 |
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC9239
Figure 4. Serial Interface Timing Diagram
Power Supply Filtering
The MPC9239 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL pin impacts the device characteristics. The
MPC9239 provides separate power supplies for the digital
circuitry (VCC) and the internal PLL (VCC_PLL) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
power supply filter scheme. The MPC9239 is most
susceptible to noise with spectral content in the 1 kHz to
1 MHz range. Therefore, the filter should be designed to
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop that will be seen
between the VCC supply and the MPC9239 pin of the
MPC9239. From the data sheet, the VCC_PLLcurrent (the
current sourced through the VCC_PLL pin) is maximum
20 mA, assuming that a minimum of 2.835 V must be
maintained on the VCC_PLL pin. The resistor shown in
Figure 5 must have a resistance of 10-15
to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. Generally, the resistor/capacitor filter
will be cheaper, easier to implement and provide an adequate
level of supply filtering. A higher level of attenuation can be
achieved by replacing the resistor with an appropriate valued
inductor. A 1000
H choke will show a significant impedance
at 10 kHz frequencies and above. Because of the current
draw and the voltage that must be maintained on the VCC_PLL
pin, a low DC resistance inductor is required (less than 15
).
Figure 5. VCC_PLL Power Supply Filter
Table 10. Test and Debug Configuration for TEST
T[2:0]
TEST Output
T2
T1
T0
0
12-bit shift register out(1)
1. Clocked out at the rate of S_CLOCK.
0
1
Logic 1
0
1
0
fXTAL ÷ 2
0
1
M-Counter out
1
0
fOUT
1
0
1
Logic 0
1
0
M-Counter out in PLL-bypass mode
1
fOUT ÷ 4
Table 11. Debug Configuration for PLL Bypass(1)
1. T[2:0] = 110. AC specifications do not apply in PLL bypass
mode.
Output
Configuration
fOUT
S_CLOCK
÷ N
TEST
M-Counter out(2)
2. Clocked out at the rate of S_CLOCK
÷ (2 N)
S_CLOCK
S_DATA
S_LOAD
M[6:0]
N[1:0]
P_LOAD
T2
T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
M, N
First
Bit
Last
Bit
VCC_PLL
VCC
MPC9239
C1, C2 = 0.01...0.1 F
VCC
CF = 22 F
RF = 10-15
C2
C1
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