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參數(shù)資料
| 型號(hào)： | MPC92429FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 400 MHz Low Voltage PECL Clock Synthesizer |
| 中文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 216K |
| 代理商： | MPC92429FN |
MPC92429
MOTOROLA
TIMING SOLUTIONS
8
Figure 4. Serial Interface Timing Diagram
S_CLOCK
S_DATA
S_LOAD
M[8:0]
N[1:0]
P_LOAD
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
M, N
First
Bit
Last
Bit
Power Supply Filtering
TheMPC92429is amixed analog/digitalproduct.Itsanalog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the powersupply pins.Random noise on
the VCC_PLL pin impacts the device characteristics. The
MPC92429 provides separate power supplies for the digital
circuitry (VCC) and the internalPLL (VCC_PLL)of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board, this level of
isolationissufficient.However,inadigitalsystemenvironment
where it is more difficult to minimize noise on the power
supplies a second level of isolation may be required. The
simplest form of isolation is a power supply filter on the
VCC_PLL pin for the MPC92429. Figure 5 illustrates a typical
power supply filter scheme. The MPC92429 is most
susceptible to noise with spectral content in the 1 kHz to
1 MHzrange.Therefore,the filtershould bedesigned totarget
this range.The key parameter thatneeds to be metin the final
filter design is the DC voltage drop that will be seen between
the VCC supply and the MPC92429 pin of the MPC92429.
From the data sheet, the VCC_PLL current (the current
sourced through the VCC_PLL pin) is maximum 20 mA,
assuming that a minimum of 2.835 V must be maintained on
the VCC_PLL pin. The resistor shown in Figure 5 must have
a resistance of 10-15
to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the
series resonant point of an individual capacitor its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures thata lowimpedance path to ground exists for
frequencies well above the bandwidth of the PLL. Generally,
theresistor/capacitorfilterwillbecheaper,easiertoimplement
andprovideanadequatelevelofsupplyfiltering.Ahigherlevel
of attenuation can be achieved by replacing the resistor with
an appropriate valued inductor. A 1000
μ
H choke will show a
significant impedance at 10 kHz frequencies and above.
Because of the current draw and the voltage that must be
maintainedontheVCC_PLL pin,a lowDCresistanceinductor
is required (less than 15
).
Figure 5. V
CC PLL
Power Supply Filter
VCC_PLL
V
CC
MPC92429
C
1
, C
2
= 0.01...0.1
μ
F
V
CC
C
F
= 22
μ
F
R
F
= 10--15
C
2
C
1
Layout Recommendations
The MPC92429 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representative board layout for the
MPC92429. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 6 is the low impedance connections
between VCCand GNDforthebypass capacitors.Combining
good quality general purpose chip capacitors with good PCB
layouttechniques willproduce effective capacitorresonances
at frequencies adequate to supply the instantaneous
switching current for the MPC92429 outputs. It is imperative
that low inductance chip capacitors are used; it is equally
important that the board layout does not introduce back all of
the inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors. Note the dotted lines circling
the crystaloscillatorconnection to the device.The oscillatoris
a series resonant circuit and the voltage amplitude across the
crystal is relatively small. It is imperative that no actively
switching signals cross under the crystal as crosstalk energy
coupled to these lines could significantlyimpactthejitterofthe
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on–board oscillator. Although the MPC92429
has several design features to minimize the susceptibility to
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| MPC92432 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1360 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92432AE | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92432AER2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92432FA | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1360 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92433 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:1428 MHz Dual Output LVPECL Clock Synthesizer |
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