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參數(shù)資料
| 型號(hào)： | MPC930FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MPC930FA |
MPC930 MPC931
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
56
the differences between the nominal delays must also be ac-
counted for.
When using the MPC931 as a zero delay buffer there is
more information which can help minimize the overall timing
uncertainty. To fully minimize the specified uncertainty, it is cru-
cial that the relative position of the outputs be known. It is rec-
ommended that if all of the outputs are going to be used that
the Qc0 output be used as the feedback reference. The Qc0
output lies in the middle of the other outputs with respect to
output skew. Therefore it can be assumed that the output to
output skew of the device is
±150ps with respect to output Qc0.
There will be some cases where only a subset of the outputs
of the MPC931 are required. There is significantly tighter skew
performance between outputs on a common bank (i.e., Qa0 to
Qa1). The skews between these common bank outputs are
outlined in the table below. In general the skews between out-
puts on a given bank is about a third of the skew between all
banks, reducing the skew to a value of 100ps.
Table 3. Within–Bank Skews
Outputs
Relative Skews
Qa0
→ Qa1
+35ps,
±50ps
Qb0
→ Qb1
–30ps,
±50ps
Qc0
→ Qc1
20ps,
±50ps
Jitter Performance of the MPC930/931
With the clock rates of today’s digital systems continuing to
increase more emphasis is being placed on clock distribution
design and management. Among the issues being addressed
is system clock jitter and how that affects the overall system
timing budget. The MPC930/931 was designed to minimize
clock jitter by employing a differential bipolar PLL as well as
incorporating numerous power and ground pins in the design.
The following few paragraphs will outline the jitter performance
of the MPC930/931, illustrate the measurement limitations and
provide guidelines to minimize the jitter of the device.
The most commonly specified jitter parameter is cycle–to–
cycle jitter. Unfortunately with today’s high performance mea-
surement equipment there is no way to measure this parame-
ter for jitter performance in the class demonstrated by the
MPC930/931. As a result different methods are used which
approximate cycle–to–cycle jitter. The typical method of mea-
suring the jitter is to accumulate a large number of cycles,
create a histogram of the edge placements and record peak–
to–peak as well as standard deviations of the jitter. Care must
be taken that the measured edge is the edge immediately fol-
lowing the trigger edge. If this is not the case the measurement
inaccuracy will add significantly to the measured jitter. The os-
cilloscope cannot collect adjacent pulses, rather it collects data
from a very large sample of pulses. It is safe to assume that
collecting pulse information in this mode will produce jitter val-
ues somewhat larger than if consecutive cycles were mea-
sured, therefore, this measurement will represent an upper
bound of cycle–to–cycle jitter. Most likely, this is a conservative
estimate of the cycle–to–cycle jitter.
1
212
12
Peak-to-Peak PLL Jitter
Peak-to-Peak Period Jitter
Figure 11. PLL Jitter and Edge Displacement
123
2
12
3
Peak-to-Peak PLL Jitter
Peak-to-Peak Period Jitter
There are two sources of jitter in a PLL based clock driver,
the commonly known random jitter of the PLL and the less
intuitive jitter caused by synchronous, different frequency out-
puts switching. For the case where all of the outputs are
switching at the same frequency the total jitter is exactly equal
to the PLL jitter. In a device, like the MPC930/931, where a
number of the outputs can be switching synchronously but at
different frequencies a “multi–modal” jitter distribution can be
seen on the highest frequency outputs. Because the output
being monitored is affected by the activity on the other outputs
it is important to consider what is happening on those other
outputs. From Figure 11, one can see for each rising edge on
the higher frequency signal the activity on the lower frequency
signal is not constant. The activity on the other outputs tends to
alter the internal thresholds of the device such that the place-
ment of the edge being monitored is displaced in time. Be-
cause the signals are synchronous the relationship is periodic
and the resulting jitter is a compilation of the PLL jitter superim-
posed on the displaced edges. When histograms are plotted
the jitter looks like a “multi–modal” distribution as pictured in
Figure 11 on page 56. Depending on the size of the PLL jitter
and the relative displacement of the edges the “multi–modal”
distribution will appear truly “multi–modal” or simply like a “fat”
Gaussian distribution. Again note that in the case where all the
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MPC931 | 制造商:Motorola Inc 功能描述: |
| MPC9315 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:2.5V and 3.3V CMOS PLL Clock Generator and Driver |
| MPC9315AC | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9315FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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