- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9025 > MPC93H51ACR2 (IDT, Integrated Device Technology Inc)IC PLL CLK DRIVER LV 32-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC93H51ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DRIVER LV 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:11 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC93H51 REVISION 4 FEBRUARY 15, 2013
8
2013 Integrated Device Technology, Inc.
MPC93H51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCCA) of the device.The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93H51.
Figure 6 illustrates a typical power supply filter scheme.
The MPC93H51 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor RF. From the data sheet the ICCA current (the current
sourced through the VCCA pin) is typically 6 mA (12 mA
maximum), assuming that a minimum of 3.0 V must be
maintained on the VCCA pin. The resistor RF shown
in Figure 6 must have a resistance of 5–15
to meet the
voltage drop criteria.
Figure 6. VCCA Power Supply Filter
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93H51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
The MPC93H51 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC 2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93H51 clock driver. For the series
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 7 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93H51 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 7. Single versus Dual Transmission Lines
The waveform plots in Figure 8 show the simulation results
of an output driving a single line versus two lines. In both
cases, the drive capability of the MPC93H51 output buffer is
more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93H51. The output
waveform in Figure 8 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36
series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL =VS (Z0 (RS + R0 + Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 (18 + 17 + 25)
= 1.31 V
At the load end, the voltage will double to 2.6 V due to the
near unity reflection coefficient. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
VCCA
VCC
MPC93H51
0.01
F
22
F
RF
VCC
0.01
F
10
IN
MPC93H51
Output
Buffer
RS = 36
ZO = 50
OutA
10
IN
MPC93H51
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9351FAR2 | IC PLL CLOCK DRIVER LV 32-LQFP |
| VE-B3D-MV-F1 | CONVERTER MOD DC/DC 85V 150W |
| VE-B3B-MV-F4 | CONVERTER MOD DC/DC 95V 150W |
| MPC9351ACR2 | IC PLL CLOCK DRIVER LV 32-LQFP |
| IDT23S09E-1HPGGI8 | IC CLK BUFFER ZD HI DRV 16-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H51FA | 功能描述:IC PLL CLK DVR HI-DRIVE 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC93H52AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。