參數(shù)資料
型號(hào): MPC93R51AC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, LEAD FREE, LQFP-32
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 339K
代理商: MPC93R51AC
Advanced Clock Drivers Devices
10
Freescale Semiconductor
MPC93R51
Figure 12. Propagation Delay (tPD, Static Phase
Offset) Test Reference
Figure 13. Propagation Delay (tPD) Test Reference
Figure 14. Output Duty Cycle (DC)
Figure 15. Output-to-Output Skew tSK(O)
VCC
VCC ÷ 2
GND
t()
PCLK
Ext_FB
PCLK
VCMR
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
TCLK
Ext_FB
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
VCC
VCC ÷ 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 16. Cycle-to-Cycle Jitter
Figure 18. I/O Jitter
Figure 19. Transition Time Test Reference
tF
tR
VCC=3.3 V
2.4
0.55
TJIT() = |T0–T1mean|
TCLK
(PCLK)
Ext_FB
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
TJIT(PER) = |TN–1/f0|
T0
Figure 17. Period Jitter
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