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參數資料
| 型號： | MPC950FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 180 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數： | 5/10頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MPC950FAR2 |
MPC950
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
153
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
Condition
tr, tf
TCLK Input Rise/Falls
3.0
ns
fref
Reference Input Frequency
Note 1.
MHz
fXtal
Crystal Oscillator Frequency
10
25
MHz
Note 2.
frefDC
Reference Input Duty Cycle
25
75
%
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK inputs.
2. See Applications Info section for more crystal information.
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
0.10
1.0
ns
0.8 to 2.0V, Note
1.
tpw
Output Duty Cycle
tCYCLE/2–1000
tCYCLE/2+1000
ps
Note 1.
tsk(O)
Output–to–Output Skews Same Frequencies
200
375
ps
Note 1.
Different Frequencies
Qafmax < 150MHz
Qafmax > 150MHz
325
500
750
fVCO
PLL VCO Lock Range
200
480
MHz
fmax
Maximum Output
Qa (
÷2)
Frequency
Qa/Qb (
÷4)
Qb (
÷8)
180
120
60
MHz
Note 1.
tPLZ,HZ
Output Disable Time
7
ns
Note 1.
tPZL
Output Enable Time
6
ns
Note 1.
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
±100
ps
Note 2.
tlock
Maximum PLL Lock Time
10
ms
1. Termination of 50
W to VCC/2.
2. See Applications Info section for more jitter information.
APPLICATIONS INFORMATION
Programming the MPC950
The MPC950 clock driver outputs can be configured into
several frequency relationships. The output dividers for the
four output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even divid-
ers ensures that the output duty cycle is always 50%. Table 1
illustrates the various output configurations, the table de-
scribes the outputs using the VCO frequency as a reference.
As an example for a 4:2:1 relationship the Qa outputs would be
set at VCO/2, the Qb’s and Qc’s at VCO/4 and the Qd’s at
VCO/8. These settings will provide output frequencies with a
4:2:1 relationship.
The division settings establish the output relationship, but
one must still ensure that the VCO will be stable given the
frequency of the outputs desired. The feedback frequency
should be used to situate the VCO into a frequency range in
which the PLL will be stable. The design of the PLL is such that
for output frequencies between 25 and 180MHz the MPC950
can generally be configured into a stable region.
The relationship between the input reference and the output
frequency is also very flexible. Table 2 shows the multiplication
factors between the inputs and outputs for the MPC950.
Figure 1 through Figure 4 illustrates several programming pos-
sibilities, although not exhaustive it is representative of the po-
tential applications.
2
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