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參數(shù)資料
| 型號(hào)： | MPC953 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器（低壓鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 104K |
| 代理商： | MPC953 |
MPC953
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3
MOTOROLA
DC CHARACTERISTICS
(TA = 0
°
to 70
°
C, VCC = 3.3V
±
5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
VIL
VPP
VCMR
VOH
VOL
IIN
CIN
Cpd
ICC
ICCPLL
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC953 outputs can drive series or parallel terminated (50
to VCC/2) 50
transmission lines on the incident edge (see Applications Info
section).
Input HIGH Voltage LVCMOS Inputs
2.0
3.6
V
Input LOW Voltage LVCMOS Inputs
0.8
V
Peak–to–Peak Input Voltage
PECL_CLK
300
1000
mV
Common Mode Range
PECL_CLK
VCC–1.5
VCC–0.6
VCC–0.6
mV
Note 1.
Output HIGH Voltage
V
IOH = –20mA, Note 2.
IOL = 20mA, Note 2.
Output LOW Voltage
0.6
V
Input Current
±
120
μ
A
Input Capacitance
4
pF
Power Dissipation Capacitance
25
pF
Per Output
Maximum Quiescent Supply Current
75
mA
All VCC Pins
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
PLL INPUT REFERENCE CHARACTERISTICS
(TA = 0 to 70
°
C)
Symbol
Characteristic
Min
Max
Unit
Condition
fref
frefDC
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
Reference Input Frequency
25
110
MHz
Note 3.
Reference Input Duty Cycle
25
75
%
AC CHARACTERISTICS
(TA = 0
°
C to 70
°
C, VCC = 3.3V
±
5%
)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
tpw
tsk(O)
fVCO
fmax
Output Rise/Fall Time
0.1
1.0
ns
0.8 to 2.0V, Note 6.
Output Duty Cycle
45
50
55
%
Note 6.
Output–to–Output Skews
150
ps
Note 6.
PLL VCO Lock Range
200
500
MHz
Note 6.
Maximum Output Frequency
PLL Mode
PLL Mode
Bypass Mode
25
50
62.5
110
200
MHz
MHz
MHz
VCO_SEL = ’1’
VCO_SEL = ’0’
Note 6.
tpd(lock)
Input to FB_CLK Delay (with PLL Locked)
–75
125
ps
Note 4., 6.
tpd(bypass)
Input to Q Delay
3
7
ns
PLL Bypassed
N t 5 6
Note 5., 6.
Part–to–Part Delay
1.5
ns
tPLZ,HZ
tPZL
tjitter
tlock
4. tpd(lock) is input reference frequency dependent. The tpd is specified at 50MHz ref, feedback
5. For a specified temperature and voltage, includes output skew.
6. Termination of 50 to VCC/2.
Output Disable Time
7
ns
Note 6.
Output Enable Time
6
ns
Note 6.
Cycle–to–Cycle Jitter
100
ps
Note 6.
Maximum PLL Lock Time
10
ms
8. The tpd does not include jitter.
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