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參數(shù)資料
| 型號(hào)： | MPG5374X |
| 元件分類： | LED |
| 英文描述： | T-1 3/4 SINGLE COLOR LED, GREEN, 5 mm |
| 封裝： | ROHS COMPLIANT PACKAGE-2 |
| 文件頁(yè)數(shù)： | 17/32頁(yè) |
| 文件大小： | 413K |
| 代理商： | MPG5374X |
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24
XMEGA C3 [DATASHEET]
8361D–AVR–07/2013
12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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