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型號(hào)：	MQ80C154-30P883D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 30 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	61/839頁(yè)
文件大?。?/td>	61013K
代理商：	MQ80C154-30P883D

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]

8285E–AVR–02/2013

However, the receive buffering has two improvements that will affect the compatibility in some special cases:

A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore

the UDRn must only be read once for each incoming data! More important is the fact that the Error Flags (FEn

and DORn) and the ninth data bit (RXB8n) are buffered with the data in the receive buffer. Therefore the status

bits must always be read before the UDRn Register is read. Otherwise the error status will be lost since the buffer

state is lost

The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to

remain in the serial Shift Register (see Figure 20-1) if the Buffer Registers are full, until a new start bit is detected.

The USART is therefore more resistant to Data OverRun (DORn) error conditions

The following control bits have changed name, but have same functionality and register location:

CHR9 is changed to UCSZn2

OR is changed to DORn

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four

modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave

synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asyn-

chronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in

the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCK pin

(DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is

only active when using synchronous mode.

Figure 20-2 shows a block diagram of the clock generation logic.

Figure 20-2. Clock Generation Logic, block diagram.

Signal description:

Transmitter clock (Internal Signal).

Receiver base clock (Internal Signal).

Input from XCK pin (internal Signal). Used for synchronous slave

Clock output to XCK pin (Internal Signal). Used for synchronous master

XTAL pin frequency (System Clock).

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The

description in this section refers to Figure 20-2.

Down-Counter

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