114
32000D–04/2011
AVR32
9.3.9
Data Transfer
9.3.9.1
Move/Load Immediate operations
9.3.9.2
Load/Store operations
Table 9-9.
Move/Load Immediate Operations
Mnemonics
Operands / Syntax
Description
Operation
Rev
mov
CRd, imm
Load immediate into register.
Rd
← SE(imm8)
1
E
Rd, imm
Rd
← SE(imm21)
1
C
Rd, Rs
Copy register.
Rd
← Rs
1
mov{cond4}
E
Rd, Rs
Copy register if condition is true
if (cond4) Rd
← Rs
1
ERd, imm
Load immediate into register if condition is
true
if (cond4) Rd
← SE(imm8)
1
movh
E
Rd, imm
Load immediate into high halfword of
register.
Rd
← imm16<<16
2
Table 9-10.
Load/Store Operations
Mnemonics
Operands / Syntax
Description
Operation
Rev
ld.ub
C
Rd, Rp++
Load unsigned byte with post-increment.
Rd
← ZE(*(Rp++))
1
C
Rd, --Rp
Load unsigned byte with pre-decrement.
Rd
← ZE(*(--Rp))
1
C
Rd, Rp[disp]
Load unsigned byte with displacement.
Rd
← ZE(*(Rp+ZE(disp3)))
1
E
Rd, Rp[disp]
Rd
← ZE(*(Rp+SE(disp16)))
1
E
Rd, Rb[Ri<<sa]
Indexed Load unsigned byte.
Rd
← ZE(*(Rb+(Ri << sa2)))
1
ld.ub{cond4}
E
Rd, Rp[disp]
Load unsigned byte with displacement if
condition satisfied.
if {cond4}
Rd
← ZE(*(Rp+ZE(disp9)))
2
ld.sb
E
Rd, Rp[disp]
Load signed byte with displacement.
Rd
← SE(*(Rp+SE(disp16)))
1
E
Rd, Rb[Ri<<sa]
Indexed Load signed byte.
Rd
← SE(*(Rb+(Ri << sa2)))
1
ld.sb{cond4}
E
Rd, Rp[disp]
Load signed byte with displacement if
condition satisfied.
if {cond4}
Rd
← SE(*(Rp+ZE(disp9)))
2
ld.uh
CRd, Rp++
Load unsigned halfword with post-
increment.
Rd
← ZE(*(Rp++))
1
C
Rd, --Rp
Load unsigned halfword with pre-
decrement.
Rd
← ZE(*(--Rp))
1
C
Rd, Rp[disp]
Load unsigned halfword with
displacement.
Rd
← ZE(*(Rp+(ZE(disp3)<<1)))
1
E
Rd, Rp[disp]
Rd
← ZE(*(Rp+(SE(disp16))))
1
E
Rd, Rb[Ri<<sa]
Indexed Load unsigned halfword.
Rd
← ZE(*(Rb+(Ri << sa2)))
1
ld.uh{cond4}
E
Rd, Rp[disp]
Load unsigned halfword with
displacement if condition satisfied.
if {cond4}
Rd
← ZE(*(Rp+ZE(disp9<<1)))
2