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參數(shù)資料
| 型號： | MQ80C32E-12SHXXX:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 2/91頁 |
| 文件大?。?/td> | 19688K |
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107
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn
(WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count
direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and
frequency correct PWM mode is shown on Figure 13-9. The figure shows phase and frequency correct PWM mode when
OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-
slope operation. The diagram includes non-inverted and inverted PWM outputs.
The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx
interrupt flag will be set when a compare match occurs.
Figure 13-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOVn) is set at the same timer clock cycle as the OCRnx registers are updated with the
double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set
when TCNTn has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between the
TCNTn and the OCRnx.
As Figure 13-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the
OCRnx registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives
symmetrical output pulses and is therefore frequency correct.
Using the ICRn register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA register is free to
be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP
value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting
the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the
COMnx1:0 to three (See Table on page 111). The actual OCnx value will only be visible on the port pin if the data direction for
the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx register at the
compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx register at
compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using
phase and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
1
2
34
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
Period
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/ TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
f
OCnxPFCPWM
f
clk_I/O
2 NTOP
----------------------------
=
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