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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
8.
System clock and their distribution
8.1
Clock systems and their distribution
Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using
detailed below.
Figure 8-1.
Clock distribution.
8.1.1
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such mod-
ules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer.
Halting the CPU clock inhibits the core from performing general operations and calculations.
8.1.2
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, UART. The I/O clock is also
used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic,
allowing such interrupts to be detected even if the I/O clock is halted.
8.1.3
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the
CPU clock.
8.1.4
PLL Clock – clk
PLL
The PLL clock allows the fast peripherals to be clocked directly from a 64/32MHz clock. A 16MHz clock is also
derived for the CPU.
General I/O
modules
ADC
CPU core
RAM
clk
I/O
AVR clock
control unit
clk
CPU
Flash and
EEPROM
clk
FLASH
clk
ADC
Source Clock
Watchdog timer
Watchdog
oscillator
Reset logic
Clock
multiplexer
Watchdog Clock
Calibrated RC
oscillator
(Crystal
oscillator)
External clock
Fast
peripherals
PLL
CLK
PLL