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參數(shù)資料
| 型號： | MQ80C32E-20SHXXX:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 57/80頁 |
| 文件大?。?/td> | 5152K |
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257
XMEGA A [MANUAL]
8077I–AVR–11/2012
23.4.1 Key and State Memory
The AES key and state memory are both 16 x 8-bit memories that are accessible through the KEY and STATE registers,
respectively.
Each memory has two 4-bit address pointers used to address the memory for read and write, respectively. The initial
value of the pointers is zero. After a read or write operation to the STATE or KEY register, the appropriate pointer is
automatically incremented. Accessing (read or write) the control register (CTRL) will reset all pointers to zero. A pointer
overflow (a sequential read or write done more than 16 times) will also set the affected pointer to zero. The pointers are
not accessible from software. Read and write memory pointers are both incremented during write operations in XOR
mode.
Access to the KEY and STATE registers is possible only when encryption/decryption is not in progress.
Figure 23-2. The state memory with pointers and register.
The state memory contains the AES state throughout the encryption/decryption process. The initial value of the state is
the initial data (i.e., plaintext in the encryption mode, and ciphertext in the decryption mode). The last value of the state is
the encrypted/decrypted data.
Figure 23-3. The key memory with pointers and register.
In the AES crypto module, the following definition of the key is used:
In encryption mode, the key is the one defined in the AES standard.
4-bit state write
address pointer
1
-
14
15
STATE
0
4-bit state read
address pointer
Reset pointer
reset or access
to AES Control
reset or access
to AES Control
STATE[read pointer]
xor
XOR
I/O Data Bus
4-bit key write
address pointer
1
-
14
15
KEY
0
4-bit key read
address pointer
Reset pointer
reset or
access to CTRL
reset or
access to CTRL
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