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參數(shù)資料
| 型號： | MQ80C32E-20SHXXX:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 73/80頁 |
| 文件大?。?/td> | 5152K |
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273
XMEGA A [MANUAL]
8077I–AVR–11/2012
These bits select EBI interface mode and the number of ports that should be enabled and overridden for EBI, according
Table 24-10. EBI mode.
24.9.2 SDRAMCTRLA – SDRAM Control register A
Bit 7:4 – Reserved
These bits are unused and reserved for future use.
Bit 3 – SDCAS: SDRAM CAS Latency
This bit sets the CAS latency as a number of ClkPER2 cycles. By default this bit is zero and the CAS latency is two ClkPER2
cycles. When this bit is set to one, the CAS latency is three ClkPER2 cycles.
Table 24-11. SDRAM CAS latency.
Bit 2 – SDROW: SDRAM Row Bits
This bit sets the number of row bits used for the connected SDRAM. By default this bit is zero, and the row bit setting is
set to 11 row bits. When this bit is set to one, the row bit setting is set to 12 row bits.
Table 24-12. SDRAM row bits.
Bit 1:0 – SDCOL[1:0]: SDRAM Column Bits
These bits select the number of column bits that are used for the connected SDRAM according to table. Table 24-13.
IFMODE[1:0]
Group Configuration
Description
00
DISABLED
EBI disabled
01
3PORT
EBI enabled with three-port interface
10
-
Reserved
11
2PORT
EBI enabled with two-port interface
Bit
7
6
5
4
3
2
1
0
+0x01
–
SDCAS
SDROW
SDCOL[1:0]
Read/Write
R
R/W
Initial Value
0
SDROW
Group configuration
Description
0
2CLK
2 ClkPER2 cycles delay
1
3CLK
3 ClkPER2 cycles delay
SDROW
Group configuration
Description
0
11BIT
11 row bits
1
12BIT
12 row bits
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