96
32059L–AVR32–01/2012
AT32UC3B
12.7 Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Inter-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantics of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 12-2.
Interrupt Request Signal Map
Group
Line
Module
Signal
00
AVR32 UC CPU with optional MPU and
optional OCD
SYSREG COMPARE
1
0
External Interrupt Controller
EIC 0
1
External Interrupt Controller
EIC 1
2
External Interrupt Controller
EIC 2
3
External Interrupt Controller
EIC 3
4
External Interrupt Controller
EIC 4
5
External Interrupt Controller
EIC 5
6
External Interrupt Controller
EIC 6
7
External Interrupt Controller
EIC 7
8
Real Time Counter
RTC
9
Power Manager
PM
2
0
General Purpose Input/Output Controller
GPIO 0
1
General Purpose Input/Output Controller
GPIO 1
2
General Purpose Input/Output Controller
GPIO 2
3
General Purpose Input/Output Controller
GPIO 3
4
General Purpose Input/Output Controller
GPIO 4
5
General Purpose Input/Output Controller
GPIO 5
3
0
Peripheral DMA Controller
PDCA 0
1
Peripheral DMA Controller
PDCA 1
2
Peripheral DMA Controller
PDCA 2
3
Peripheral DMA Controller
PDCA 3
4
Peripheral DMA Controller
PDCA 4
5
Peripheral DMA Controller
PDCA 5
6
Peripheral DMA Controller
PDCA 6
4
0
Flash Controller
FLASHC
50
Universal Synchronous/Asynchronous
Receiver/Transmitter
USART0