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型號(hào)：	MQ80C52CXXX-36/883:RD
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	154/1021頁(yè)
文件大小：	15196K

32072H–AVR32–10/2012

AT32UC3A3

DBW: Data Bus Width

BAT: Byte Access Type

This field is used only if DBW defines a 16-bit data bus.

EXNWMODE: External WAIT Mode

The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the

read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for

the read and write controlling signal.

WRITEMODE: Write Mode

1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be

inserted after the setup of NWE.

0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be

inserted after the setup of NCS.

Data Bus Width

Byte Access Type

Byte select access type:

Write operation is controlled using NCS, NWE, NBS0, NBS1

Read operation is controlled using NCS, NRD, NBS0, NBS1

Byte write access type:

Write operation is controlled using NCS, NWR0, NWR1

Read operation is controlled using NCS and NRD

EXNWMODE

External NWAIT Mode

the NWAIT input signal is ignored on the corresponding chip select.

Frozen Mode:

if asserted, the NWAIT signal freezes the current read or write cycle. after deassertion, the read or write cycle

is resumed from the point where it was stopped.

the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read

or write signal, to complete the access. If high, the access normally completes. If low, the access is extended

until NWAIT returns high.

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