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參數(shù)資料
| 型號： | MQ80C52EXXX-20/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 101/219頁 |
| 文件大?。?/td> | 7896K |
| 代理商： | MQ80C52EXXX-20/883D |
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19
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero dis-
ables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is
set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is
zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit
to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are cor-
rectly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be
written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following pro-
cedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1.
Wait until EEWE becomes zero.
2.
Wait until SPMEN in SPMCR becomes zero.
3.
Write new EEPROM address to EEAR (optional).
4.
Write new EEPROM data to EEDR (optional).
5.
Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the
Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software con-
tains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 194 for details about
boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write
Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the
EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to
have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before
the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in
the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read
access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the
CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither
possible to read the EEPROM, nor to change the EEAR Register.
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