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參數(shù)資料
| 型號： | MQ80C52EXXX-25SBR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 3152K |
| 代理商： | MQ80C52EXXX-25SBR |
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6
7707F–AVR–11/10
AT90USB82/162
2.2.4
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of various special features of the AT90USB82/162 as listed on
2.2.5
Port D (PD7..PD0)
Port D serves as analog inputs to the analog comparator.
Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-
cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
2.2.6
D-/SDATA
USB Full Speed Negative Data Upstream Port / Data port for PS/2
2.2.7
D+/SCK
USB Full Speed Positive Data Upstream Port / Clock port for PS/2
2.2.8
UGND
USB Ground.
2.2.9
UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.10
UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1F).
2.2.11
RESET/PC1/dW
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Section 9.. Shorter
pulses are not guaranteed to generate a reset. This pin alternatively serves as debugWire chan-
nel or as generic I/O. The configuration depends on the fuses RSTDISBL and DWEN.
2.2.12
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.13
XTAL2/PC0
Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.
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