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參數(shù)資料
| 型號(hào)： | MQ80C52TXXX-20:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 256/313頁(yè) |
| 文件大?。?/td> | 4988K |
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47
32000D–04/2011
AVR32
5.3
Operation of the MMU and MMU exceptions
The MMU uses both hardware and software mechanisms in order to perform its memory remap-
ping operations. The following tasks are performed by hardware:
1.
The MMU decodes the virtual address and tries to find a matching entry in the TLB.
This entry is used to generate a physical address. If no matching entry is found, a TLB
miss exception is issued.
2.
The matching entry is used to determine whether the access has the appropriate
access rights, cacheability, bufferability and so on. If the access is not permitted, a TLB
Protection Violation exception is issued.
3.
If any other event arises that requires software intervention, an appropriate exception is
issued.
4.
If the correct entry was found in the TLB, and the access permissions were not violated,
the memory access is performed without any further software intervention.
The following tasks must be performed by software:
1.
Setup of the MMU hardware by initializing the MMU-related registers and data struc-
tures if needed.
2.
Maintenance of the TLB structure. TLB entries are written, invalidated and replaced by
means of software. A tlbw instruction is included in the instruction set to support this.
3.
The MMU may generate several exceptions. Software exception handlers must be writ-
ten in order to service these exceptions.
5.3.1
The tlbw instruction
The tlbw instruction is implemented in order to aid in performing TLB maintenance. The instruc-
tion copies the contents of TLBEHI and TLBELO into the TLB entry pointed to by the ITLB or
DTLB Replacement Pointers (IRP/DRP) in the MMU Control Register. The TLBEHI[I] bit decides
if the ITLB or the DTLB should be addressed. IRP and DRP may in some implementations be
automatically updated by hardware in order to implement a TLB replacement algorithm in hard-
ware. Software may update them before executing tlbw in order to implement a software
replacement algorithm.
In some implementations, the TLB data structures may be mapped into the P4 space. In such
implementations, the TLB data structures may be updated with regular memory access
instructions.
5.3.2
TLB synonyms
Implementations using virtually indexed caches may be subject to cache inconsistencies,
depending on the page size used and number of lines in the cache. These inconsistencies may
occur when multiple virtual addresses are mapped to the same physical address, since a trans-
lated part of VPN may be used to index the cache. This implies that the same physical address
may be mapped to different cache lines, causing cache inconsistency.
Synonym problems can only appear when addressing data residing in a virtually indexed cache.
Addressing uncached memory or accessing untranslated memory will never cause synonym
problems.
It is the responsability of the OS to define a policy ensuring that no synonym problems may
arise. No hardware support is provided to avoid TLB synonyms.
相關(guān)PDF資料 |
PDF描述 |
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| MQ80C52XXX-12/883:D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| MD80C32-20SC | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32-16/883:R | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C154-30/883R | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MQ82370-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ8238020 | 制造商:Intel 功能描述:CONTROLLER: OTHER |
| MQ82380-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ82380-20/R | 制造商:Rochester Electronics LLC 功能描述: |
| MQ82592 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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