52
32000D–04/2011
AVR32
accessed with the mtsr and mfsr instructions.
The MPU interface registers are shown below. The suffix n can have the range 0-7, indicating
which region the register is associated with.
Figure 6-1.
The MPU interface registers
6.2.1.1
MPU Address Register - MPUARn
A MPU Address register is implemented for each of the 8 protection regions. The MPUAR regis-
ters specify the start address and size of the regions. The start address must be aligned so that
its alignment corresponds to the size of the region. The minimum allowable size of a region is 4
KB, so only bits 31:12 in the base address needs to be specified. The other bits are always 0.
Each MPUAR also has a valid bit that specifies if the protection region is valid. Only valid regions
are considered in the protection testing.
The MPUAR register consists of the following fields:
Base address - The start address of the region. The minimum size of a region is 4KB, so only
the 20 most significant bits in the base address needs to be specified. The 12 lowermost
base address bits are implicitly set to 0. If protection regions larger than 4 KB is used, the
user must write the appropriate bits in Base address to 0, so that the base address is aligned
to the size of the region. Otherwise, the result is UNDEFINED.
Base Address
Size
0
5
12
31
MPUARn
-
0
31
-
8 7 6
4321
0
31
0
31
E
0
31
MPUCR
-
1
11
6
V
1
MPUCRA / MPUCRB
5
MPUBRA / MPUBRB
-
8 7 6
4321
5
MPUAPRA / MPUAPRB
AP0
AP1
AP2
AP3
AP4
AP5
AP6
AP7
3
4
7
8
11
12
15
16
19
20
23
24
27
28
-
31
MPUPSRn
P10
P11
P12
P13
P14
P15
P4
P5
P6
P7
P8
P9
P0
P1
P2
P3
0
8 7 6
4321
5
9
16 15
13 12 11 10
14
C4
C5
C6
C7
C0
C1
C2
C3
B4
B5
B6
B7
B0
B1
B2
B3