6
32000D–04/2011
AVR32
AVR32 can access data of size byte, halfword, word and doubleword using dedicated instruc-
tions. The memory system can support unaligned accesses for selected load/store instructions
in some implementations. Any other unaligned access will cause an address exception.
For performance reasons, the user should make sure that the stack always is word aligned. This
means that only word instructions can be used to access the stack. When manipulating the
stack pointer, the user has to ensure that the result is word aligned before trying to load and
store data on the stack. Failing to do so will result in performance penalties. Code will execute
correctly if the stack is unaligned but with a significant performance penalty.
2.3
Instruction Organization
The AVR32 instruction set has both compact and extended instructions. Compact instructions
denotes the instructions which have a length of 16 bits while extended instructions have a length
of 32 bits.
instructions can be both aligned and unaligned to halfword boundaries. In normal instruction
flow, the instruction buffer will always contain enough entries to ensure that compact, aligned
extended and unaligned extended instructions can be issued in a single cycle.
Change-of-flow operations such as branches, jumps, calls and returns may in some implemen-
tations require the instruction buffer to be flushed. The user should consult the Technical
Reference Manual for the specific implementation in order to determine how alignment of the
branch target address affects performance.
Table 2-2.
Instructions are stored in memory in a big endian fashion and must be aligned on
half word boundaries
Word Address
IJ
N+24
H1
H2
N+20
F2
G
N+16
E2
F1
N+12
DE1
N+8
C1
C2
N+4
AB
N
Byte Address
012
3
Byte Address
012
3