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參數(shù)資料
| 型號(hào)： | MQ83C154DXXX-16/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 190/242頁(yè) |
| 文件大?。?/td> | 3080K |
| 代理商： | MQ83C154DXXX-16/883 |
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51
2588F–AVR–06/2013
ATtiny261/461/861
0x0003
rjmp
TIM1_COMPA
; Timer1 CompareA Handler
0x0004
rjmp
TIM1_COMPB
; Timer1 CompareB Handler
0x0005
rjmp
TIM1_OVF
; Timer1 Overflow Handler
0x0006
rjmp
TIM0_OVF
; Timer0 Overflow Handler
0x0007
rjmp
USI_START
; USI Start Handler
0x0008
rjmp
USI_OVF
; USI Overflow Handler
0x0009
rjmp
EE_RDY
; EEPROM Ready Handler
0x000A
rjmp
ANA_COMP
; Analog Comparator Handler
0x000B
rjmp
ADC
; ADC Conversion Handler
0x000C
rjmp
WDT
; WDT Interrupt Handler
0x000D
rjmp
EXT_INT1
; IRQ1 Handler
0x000E
rjmp
TIM0_COMPA
; Timer0 CompareA Handler
0x000F
rjmp
TIM0_COMPB
; Timer0 CompareB Handler
0x0010
rjmp
TIM0_CAPT
; Timer0 Capture Event Handler
0x0011
rjmp
TIM1_COMPD
; Timer1 CompareD Handler
0x0012
rjmp
FAULT_PROTECTION ; Timer1 Fault Protection
0x0013
RESET: ldi
r16, low(RAMEND) ; Main program start
0x0014
ldi
r17, high(RAMEND); Tiny861 have also SPH
0x0015
out
SPL, r16
; Set Stack Pointer to top of RAM
0x0016
out
SPH, r17
; Tiny861 have also SPH
0x0017
sei
; Enable interrupts
0x0018
<instr>
...
9.2
External Interrupts
The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15:0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT15:0 pins are
configured as outputs. This feature provides a way of generating a software interrupt. Pin
change interrupts PCI will trigger if any enabled PCINT15:0 pin toggles. The PCMSK Register
control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15:0
are detected asynchronously. This implies that these interrupts can be used for waking the part
also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0
interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the
pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires
the presence of an I/O clock, described in “Clock Subsystems” on page 24.
9.2.1
Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source
can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in
all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ83C154DTXXX-20/883 | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| MR83C154DXXX-25P883R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
| MQ83C154DCXXX-25/883R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MQ83C154DCXXX-16/883 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MQ83C154DCXXX-12/883D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MQ83C154-L16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-12 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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