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| 型號(hào)： | MQ83C154DXXX-16/883 |
| 廠(chǎng)商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 32/242頁(yè) |
| 文件大?。?/td> | 3080K |
| 代理商： | MQ83C154DXXX-16/883 |
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127
2588F–AVR–06/2013
ATtiny261/461/861
Figure 13-3. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in Figure 13-3. At the top of the figure is a USCK cycle ref-
erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI
is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative
edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0 are
used. In other words, data is sampled at negative and output is changed at positive edges. The
USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 13-3), a bus transfer involves the following steps:
1.
The slave and master devices set up their data outputs and, depending on the protocol
used, enable their output drivers (mark A and B). The output is set up by writing the
data to be transmitted to the USI Data Register. The output is enabled by setting the
corresponding bit in the Data Direction Register of Port A. Note that there is not a pre-
ferred order of points A and B in the figure, but both must be at least one half USCK
cycle before point C, where the data is sampled. This is in order to ensure that the data
setup requirement is satisfied. The 4-bit counter is reset to zero.
2.
The master software generates a clock pulse by toggling the USCK line twice (C and
D). The bit values on the data input (DI) pins are sampled by the USI on the first edge
(C), and the data output is changed on the opposite edge (D). The 4-bit counter will
count both edges.
3.
Step 2. is repeated eight times for a complete register (byte) transfer.
4.
After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
the transfer has been completed. The data bytes transferred must now be processed
before a new transfer can be initiated. The overflow interrupt will wake up the processor
if it is set to Idle mode. Depending on the protocol used the slave device can now set its
output to high impedance.
13.3.2
SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer:
sts
USIDR,r16
ldi
r16,(1<<USIOIF)
sts
USISR,r16
ldi
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
MSB
654321
LSB
1
2
3
4
5
6
7
8
654321
LSB
USCK
DO
DI
D
C
B
A
E
CYCLE ( Reference )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR83C154DTXXX-20P883D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MD83C154DCXXX-16/883 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR83C154DCXXX-16/883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154DCXXX-20P883R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154DXXX-12/883 | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MQ83C154-L16 | 制造商:TEMIC 制造商全稱(chēng):TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-12 | 制造商:TEMIC 制造商全稱(chēng):TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-16 | 制造商:TEMIC 制造商全稱(chēng):TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-20 | 制造商:TEMIC 制造商全稱(chēng):TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ83C154T-25 | 制造商:TEMIC 制造商全稱(chēng):TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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