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參數(shù)資料
| 型號： | MQ83C154DXXX-20/883R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 214/242頁 |
| 文件大?。?/td> | 3080K |
| 代理商： | MQ83C154DXXX-20/883R |
73
2588F–AVR–06/2013
ATtiny261/461/861
Figure 11-2.
Prescaler for Timer/Counter0
Note:
1. The synchronization logic on the input pins (
T0) is shown in Figure 11-3.
The prescaled clock has a frequency of f
CLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. See
Table 11-4 on page 85 for details.
11.3.1.1
Prescaler Reset
The prescaler is free running, i.e. it operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count
occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,
256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to
program execution.
11.3.2
External Clock Source
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0). The
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector. Figure 11-3 shows a functional
equivalent block diagram of the T0 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (clk
I/O). The latch is transparent in the
high period of the internal system clock.
The edge detector generates one clk
T0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
= 6) edge it detects. See Table 11-4 on page 85 for details.
PSR0
Clear
clk
T0
T0
clk
I/O
Synchronization
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