126
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1
Features
Single Compare Unit Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
Allows Clocking from External 32kHz Watch XTAL Independent of the I/O Clock
18.2
Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in
Figure 18-1. For the actual placement of I/O pins,
Figure 18-1. 8-bit Timer/Counter, block diagram.
18.2.1
Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Interrupt request (shorten
as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decre-
ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clk
T2).
Timer/Counter
D
ATA
B
U
S
=
TCNTn
Waveform
Generation
OCnx
= 0
Control Logic
= 0xFF
TOP
BOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCnx
(Int.Req.)
Synchronization Unit
OCRnx
TCCRnx
ASSRn
Status flags
clk
I/O
clk
ASY
Synchronized Status flags
asynchronous mode
select (ASn)
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
Tn
clk
I/O