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32059L–AVR32–01/2012
AT32UC3B
19.10 Master Mode
19.10.1
Definition
The Master is the device which starts a transfer, generates a clock and stops it.
19.10.2
Application Block Diagram
Figure 19-5. Master Mode Typical Application Block Diagram
19.10.3
Programming Master Mode
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
to access slave devices in read or write mode.
2. CKDIV + CHDIV + CLDIV: Determines clock waveform Thigh and Tlow.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
19.10.4
Master Mode Clock Timing
The TWI module monitors the state of the TWCK line as required by the IC specification. The
counter that determines the TWCK Thigh or Tlow duration is started whenever a high or low level
is detected by the module on TWCK, not when the module begins releasing or driving the TWCK
line. Thus, the CWGR.CHDIV and CLDIV fields do not alone determine the overall TWCK
period; they merely determine the Thigh and Tlow components, whereas the rise and fall times
(Trise and Tfall) are determined by the external circuitry on the TWCK pin as well as the propaga-
tion and synchronization delay of TWCK from the pin back into the TWI module. The TWI
module does not attempt to compensate for these delays, so the overall TWI clock period is
given by Thigh+Tfall+Tlow+Trise.
19.10.5
Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register, THR,
it sends a 7-bit slave address, configured in the Master Mode register (DADR in MMR), to notify
the slave device. The bit following the slave address indicates the transfer direction, 0 in this
case (MREAD = 0 in MMR).
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM
IC RTC
IC LCD
Controller
Slave 1
Slave 2
Slave 3
VDD
IC Temp.
Sensor
Slave 4
Rp: Pull up value as given by the IC Standard
Rp