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型號：	MQ83C154TXXX-36P883R
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù)：	168/839頁
文件大?。?/td>	61013K
代理商：	MQ83C154TXXX-36P883R

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]

8285E–AVR–02/2013

EEARH and EEARL – EEPROM Address Register Atmel

ATmega325A/325PA/3250A/3250PA/625A/645P/6450A/6450P

Bits 15:11 – Reserved

These bits are reserved bits in the

ATmega325A/325PA/3250A/3250PA/645A/645P/6450A/6450P and will always read as zero.

Bits 10:0 – EEAR10:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1/2K bytes EEPROM

space. The EEPROM data bytes are addressed linearly between 0 and 1023/2047. The initial value of EEAR is

undefined. A proper value must be written before the EEPROM may be accessed.

1. EEAR10 is only valid for ATmega645A/ATmega645P/ATmega6450A/ATmega6450P.

EEDR – EEPROM Data Register

Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the

address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from

the EEPROM at the address given by EEAR.

EECR – EEPROM Control Register

Bits 7:4 – Reserved

These bits are reserved and will always read as zero.

Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero dis-

ables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is

set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is

Initial Value

Initial Value

Initial Value

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